1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor, and a capacitor structure and particularly, to a semiconductor device with a capacitor and a fabrication process therefor.
2. Description of the Background Art
A dynamic random access memory (DRAM) has been known, as a memory on which random input/output of storage information can be performed among semiconductor devices. FIG. 16 is a sectional view of a prior art DRAM. Referring to FIG. 16, the prior art DRAM includes a field effect transistor 9 and a capacitor 25 connected to the field effect transistor 9.
The field effect transistor 9 is constructed of a gate electrode 5 formed on a silicon substrate 1 with a gate oxide film 4 interposing therebetween and a region 3 including a source and a drain formed on the silicon substrate 1 on respective both sides of the gate electrode 5. Trenches la are formed in the vicinity of the field effect transistor 9 and a silicon oxide film 2 as a isolation insulating film is formed so as to fill the trenches 1a. 
An interlayer insulating film 10 made of a silicon oxide film is formed on a surface of the silicon substrate 1. A contact hole 11 extending to the source/drain region 3 is formed in the interlayer insulating film 10 and a plug layer 12 fills the contact hole 11.
The capacitor 25 is formed so as to be electrically connected to the field effect transistor 9 through the plug layer 12. The capacitor 25 is constructed of a storage node 13, a dielectric film 14 provided on the storage node 13 and a cell plate 17 provided on the dielectric film 14. An interlayer insulating film 20 is provided on the interlayer insulating film 10 so as to cover the cell plate 17 and the dielectric film 14.
A contact hole 20h is formed in the interlayer insulating film 20 and communicates with an opening 17h formed in the cell plate 17. A titanium film 21 and a titanium nitride film 22 are formed on sidewalls of the contact hole 20h and the opening 17h in contact with the sidewalls and further, a plug layer 23 made of tungsten is provided so as to be in contact with the titanium nitride film 22. An interconnect layer 24 is provided so as to be in contact with the plug layer 23. The interconnect layer 24 is electrically connected to the cell plate 17 through the plug layer 23, the titanium nitride film 22 and the titanium film 21 formed in the opening 17h. 
Description will be given of problems encountered in a prior art semiconductor device below:
In recent years, miniaturization of DRAM has progressed such that, for example, a gate length of the gate electrode 5 is 0.15 xcexcm or less and a diameter of the contact hole 20h is 0.24 xcexcm or less. With as small a diameter of the contact hole 20h as this, a diameter of the opening 17h becomes small as well, leading to a problem that a contact area between the cell plate 17 and the titanium film 21 becomes smaller and thereby electric resistance of a contact therebetween increases. When a contact resistance between the cell plate 17 and the titanium film 21 of DRAM is larger, difficulty arises in keeping a potential of the cell plate 17 at a prescribed level, again resulting in a problem of reduced reliability of a semiconductor device.
The present invention has been made in order to solve problems as described above and it is accordingly an object of the present invention to provide a high reliability semiconductor device and a high reliability capacitor structure.
A semiconductor device according to the present invention includes: a semiconductor substrate; a first conductive layer formed on the semiconductor substrate; a second conductive layer on the first conductive layer in contact therewith; and an insulating layer covering the second conductive layer. A first opening is formed in the first conductive layer. A second opening communicating with the first opening and having a diameter different from that of the first opening is formed in the second conductive layer. A connection hole communicating with the second opening is formed in the insulating layer. The semiconductor device further includes: a third conductive layer formed on the insulating layer so as to be electrically connected to the first and second conductive layers through the first and second openings.
In the semiconductor device having such a structure, a step arises between the first and second openings because of a difference in diameter between the first and second openings. Alternatively, a tapered portion arises therebetween. Since the third conductive layer is electrically connected to the first and second conductive layers through the first and second openings, combined contact areas of the third conductive layer with the first and second conductive layers increase. As a result, a contact resistance therebetween decreases, thereby enabling enhanced reliability of a semiconductor device.
It is preferable that a diameter of the second opening is larger than that of the first opening. In this case, the first and second openings are of a combined shape tapered in the depth direction and as a result, the third conductive layer fills the first and second openings with ease.
It is preferable that the first opening has a bottom surface. In this case, the first and third conductive layers are in contact with each other; therefore, more of a contact area is ensured. As a result, a contact resistance can be further reduced.
It is preferable that the third conductive layer includes a plug layer filling a connection hole and electrically connected to the first and second conductive layers.
It is preferable that the first and second conductive layers are made of respective materials different from each other.
It is preferable that the first and second conductive layers are formed by means of respective methods different from each other.
It is preferable that the first conductive layer is a titanium nitride film formed by means of a chemical vapor deposition method and the second conductive layer is a titanium nitride formed by means of a sputtering method.
It is preferable that the first and second conductive layers each include first and second elements and a ratio of the first element to the second element in the first conductive layer is different from a ratio of the first element to the second element in the second conductive layer.
It is preferable that the first conductive layer constitutes a cell plate of a capacitor of a dynamic random access memory.
A capacitor structure according to the present invention includes: a first capacitor electrode; a dielectric film formed on the first capacitor electrode; and a second capacitor electrode formed on the dielectric film. The second capacitor electrode includes: a first conductive layer; and a second conductive layer on the first conductive layer in contact therewith. The capacitor structure further includes: an insulating layer covering the second conductive layer. A first opening is formed in the first conductive layer. A second opening communicating with the first opening and having a diameter different from that of the first opening is formed in the second conductive layer. A connection hole communicating with the second opening is formed in the insulating layer. Furthermore, the capacitor structure includes: a third conductive layer formed on the insulating layer so as to be electrically connected to the first and second conductive layers through the first and second openings.
In the capacitor structure constructed in such a way, the first and second openings are different in diameter from each other. Therefore, a step arises between the first and second openings. Alternatively, a tapered portion arises therebetween. Therefore, combined areas of the third conductive layer with the first and second openings increase and contact areas combined contact areas of the third conductive layer with the first and second conductive layers increase. As a result, a contact resistance therebetween can be reduced, thereby enabling enhanced reliability of a capacitor structure.
A fabrication process for a semiconductor device according to the present invention includes the following steps:
(1) a step of forming a first conductive layer on a semiconductor substrate;
(2) a step of forming a second conductive layer on the first conductive layer in contact therewith;
(3) a step of forming an insulating layer on the second conductive layer;
(4) a step of forming a mask layer having a hole on the insulating layer;
(5) a step of etching the insulating layer and the second and first conductive layers with the mask layer as a mask to form a connection hole in the insulating layer, form a second opening having a relatively larger diameter and communicating with the connection hole in the second conductive layer and form a first opening having a relatively smaller diameter and communicating with the second opening in the first conductive layer; and
(6) a step of forming a third conductive layer so as to be electrically connected to the first and second conductive layers through the first and second openings.
According to a fabrication process for a semiconductor device including such steps, there are formed the second opening having a relatively larger diameter and the first opening having a relatively smaller diameter; therefore, a step arises between the first and second openings. Alternatively, a tapered portion arises therebetween. The third conductive layer is formed so as to be electrically connected to the first and second conductive layers through the first and second openings. Therefore, combined contact areas of the third conductive layer with the first and second conductive layers increase and thereby, a contact resistance therebetween can be reduced. As a result, a high reliability semiconductor device can be provided.
It is preferable that the etching step includes to etch the first and second conductive layers in a condition that an etching rate of the first conductive layer is smaller than that of the second conductive layer.
It is preferable that the step of forming the first conductive layer includes to form the first conductive layer by means of a first film forming method and the step of forming the second conductive layer includes to form the second conductive layer by means of a second film forming method different from the first film forming method.
It is preferable that the first film forming method is a chemical vapor deposition method and the second film forming method is a sputtering method.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description/of the present invention when taken in conjunction with the accompanying drawings.